In digital data transmission systems, composite clock and data signals in binary form are transmitted over media such as wires or fiber optic cables from a transmission line transmitter to a transmission line receiver. Data is represented by pulses in the signal stream defined by positive-going and negative-going transitions at particular times. The transmitter outputs the composite signal at a predetermined frequency. Typically, however, the phase of the composite signal of predetermined frequency is subject to phase drift or jitter (a valid transition occurring at a time other than where expected) and noise (an invalid transition).
The transmission line receiver typically includes a regenerative repeater for accurately reconstructing the transmitted data, regardless of phase drift and noise. The transmitted composite signal is thereby repeatedly reconstructed instead of becoming progressively more and more phase-shifted and noisy. In the case of long distance, high capacity digital systems, the accuracy of the regenerative repeaters will often determine the overall effectiveness of the system.
The function of the repeaters is to reconstruct the transmitted composite signal in its original form, ideally without error. Such reconstruction can be achieved by sampling the received signal at a regular rate equal to the transmitted bit rate, and at each sample instant making a decision of the most probable symbol being transmitted. Typically, a threshold level is chosen to which the received signal is compared. Above this threshold level a binary one is registered, and below the threshold a binary zero is registered.
The regenerator circuit makes these zero or one decisions, based on clocking information provided by a phase locked loop (PLL), at sampling times during which positive-going and negative-going transitions do not occur. By sampling at these selected times, the odds of accurately reconstructing the transmitted binary bits in the signal are increased, and hence the bit error rate (BER) of the ultimately reconstructed data signal is improved.
Phase locked loops in regenerator circuits provide a local clock signal at which the transmitted signal is sampled during reconstruction. Phase lock loops may be implemented in either analog or digital form. Digital phase lock loops (DPLLs) alleviate some of the problems associated with analog PLLs; namely, sensitivity to noise, difficulties encountered in constructing higher order loops, and, depending on the system, the need for initial calibration and periodic adjustments.
Known digital phase lock loops include a local oscillator for outputting a local clock signal which is compared to the received composite signal to indicate the phase difference between the local clock and the received composite signal. One such digital phase lock logic circuit is described by E. A. Zurfluh in U.S. Pat. No. 4,677,648, entitled "Digital Phase Locked Loop Synchronizer," assigned to the same assignee as the present invention and incorporated by reference herein. According to the '648 patent, a local oscillator clock signal of a given frequency is furnished to a digital delay chain which is used to both determine the phase offset between an incoming signal and a locally generated clock signal and to obtain a phase selected signal. Evaluation means, upon occurrence of a digital transition, obtains bi-level tap signal values as a phase offset indication and generates an appropriate phase selection signal which selects one of the delay line tap signals as the output clock signal. Although somewhat successful under jitter conditions, the Zurfluh technique experiences difficulty in differentiating between noise and valid data transitions, especially in a high noise environment.
The local clock signal and the received composite signal often differ in frequency, as well as phase, because each of these two signals is produced by a separate oscillator. Although the separate oscillators may be chosen and/or tuned to output clock signals of nearly identical frequency, in high speed data applications, even a small differential in frequency may result in sampling times which do not optimize reconstruction of the originally transmitted data. The resultant reconstruction may cause an unacceptable increase in the bit error rate in the regenerated data signal. Accordingly, it is believed that there is a need for providing a digital phase lock logic system which compensates for differences in both phase and frequency of a transmitted composite signal with respect to a locally generated clock signal.
It is an object of the present invention, therefore, to provide a high-speed, low-power digital phase lock logic system for (i) determining differences in the phase and frequency of a received composite signal with respect to a locally generated clock signal and (ii) extracting timing information from the received composite signal in real time based on the determination of the phase and frequency differences.